搜索资源列表
conv_vhdl
- 用Verilog实现卷积码(2,1,2)的编码器,采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
fir
- 用状态机编写的FIR,verilog代码,已经经过仿真-With the state machine written in FIR, verilog code, and has passed through simulation
verilog_example
- 九个verilog源码例子,包括寄存器,状态机等,含testbench-9 verilog source code examples, including registers, state machines, with testbench
moore
- moore状态机实验verilog代码,我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
thunderbird
- 控制左右两对灯一次点亮,用状态机实现,verolog语言编写-Control about two lit the lamp again with the state machine implementation, verolog language
verilog
- 介绍了一种硬件控制的自动数据采集系统的设计方法,包括数字系统自顶向下 (1DP—DOwN)的设计思路,Vernog}Ⅱ)L对系统硬件的描述和状态机的设计-Introduced a hardware-controlled automated data acquisition system design, including digital systems from top to bottom (1DP-DOwN) design ideas, Vernog} Ⅱ) L of the system
verilog
- 用verilog语言进行状态机的时序与功能仿真-Verilog state machine language with timing and functional simulation
Verilog-state-machine
- 状态机采用 VerilogHDL 语言编码,建议分为三个 always 段,本文档就是详述其原因-VerilogHDL language code using the state machine, the proposed section is divided into three always
adc
- 设计ADC控制器,Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器,采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
How-to-write-by-verilog
- 如何写好状态机,用verilog。状态机很方便。-How to write a state machine, with verilog. State machine is very convenient.
Verilog-FSM
- VERILOG HDL 学习有限状态机的重要PPT-VERILOG HDL FSM PPT
verilog-state-machine
- 使用VerilogHDL语言的小教程。 用三段式方法编写状态机。 有清晰详细的注释。-A small tutorial teaching how to write the state machine using three-step method in VerilogHDL language. There are clear and detailed notes in the tutorial.
AD0804
- AD0804的控制程序,有VHDL和verilog两个方式。还有AD0804的介绍,和状态机控制-AD0804 control program, there are two ways to VHDL and verilog. There AD0804 introduction, and the state machine control
verilog
- 一些基本的Verilog 代码 包括基本的分频器设计,交通灯设计,自动售货机设计,有限状态机的设计-Some basic Verilog For freshman
TLC5620v
- 本程序是用verilog 状态机编写的tlc5620的驱动程序,可以直接调用-The program is written in verilog tlc5620 state machine driver, you can directly call
11_lcd1602
- 本程序是用verilog 状态机编写的lcd1602的驱动程序,可以直接调用-The program is written in verilog lcd1602 state machine driver, you can directly call
fsm_seq_det
- verilog 状态机实现序列检测。简单明了,打开modelsim-change directory -do sim.do 即可-State machine sequence detection.
verilog
- 语言设计,虚拟器件,有限状态机,verilong语言教程等-Virtual Appliance
serial_to_para
- verilog状态机实现并串转换serial_to_para,本人已调试并仿真成功,绝对可用-verilog state machine and string conversion,i think it is very important to someone who is ready to learn verilog
fsm_seq0101
- verilog状态机实现的序列检测器,本人仿真通过,绝对可用,欢迎大家下载学习。-verilog state machine sequence detector simulation by himself, absolutely free, welcome to download the study.